Electrostatic discharge (ESD) is a momentary and sudden electric current that flows when an excess of electric charge stored on an electrically insulated structure finds a path to another structure at a different electrical potential, such as ground. The ESD protection scheme, its power consumption and efficient use of semiconductor real estate to protect integrated circuits (ICs) are particularly serious concerns with microelectronic devices. In most cases, the ICs in these devices are not repairable if affected by an ESD event. The shrinking size of modern electronics demands that ICs, complete with ESD protection, fit into a small package.
It is common in IC design to include ESD protection, in the form of a “clamping” circuit, to the terminals that receive an operating voltage for driving an IC chip, or portion thereof. A voltage clamp ensures that a sudden surge in voltage from an ESD event can be safely discharged so that no damage results to the internal active devices of the integrated circuit. The clamping circuit often includes a relatively large field-effect transistor (FET) capable of discharging the electrical current produced from an ESD event that, however brief, can result in peak voltages many times the operating voltage of the IC. When an ESD potential occurs across the power supply and ground terminals, a trigger circuit turns on the FET so as to conduct the ESD current, thereby clamping the power supply terminal voltage.
High voltage ESD clamps can be triggered based on either a rate of change of voltage (dv/dt) or an absolute value of the voltage, e.g., at a power supply terminal. Each of these types of trigger circuits has disadvantages. For example, trigger circuits that are based on the absolute value of a voltage require an element, such as a zener diode, that triggers the clamping circuit at the correct voltage. The trigger voltage must be greater than the normal operating voltage (Vdd) of the power supply but less than the breakdown voltage (Vbd) of devices connected to the power supply terminal. An ESD clamp of this type waits until the absolute value of the voltage on the power supply terminal exceeds the trigger voltage before triggering, which leaves little time and a small voltage window to operate (i.e., clamp the excessive voltage) before damaging the devices connected to the power supply. Further exasperating this configuration is the fact that high voltage applications typically include many different operational voltages (e.g., 5, 7, 12, 25, 50, and 120 V), meaning that plural trigger circuits must be tailored to each operational voltage.
Trigger circuits that are based on rate of change of voltage at the power supply terminal typically include a resistor-capacitor (RC) circuit having a time constant sufficient to keep the clamp device triggered for the duration of an ESD event. However, in some applications the normal operational rise time approaches the time constant defined by the RC-triggered circuit, which causes the trigger circuit to undesirably turn on the clamping circuit during a normal power up sequence.